SRAM-based FPGAs for safety critical applications L. Sterpone1, M. Aguirre2, J. Tombs2, H. Guzmán-Miranda2 capabilities of tunable fault tolerance techniques. In  an approach is proposed that uses selective triple modular redundancy (S-TMR) which extends the basic TMR technique by identify SEU sensitive gates given a circuit and then introducing TMR selectively at these gates. This.
Fault-tolerance techniques for sram-based fpgas pdf
In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high .
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving %.